Data Integrity and Cost of Test Challenges During Wafer Test

Developing advanced monolithic semiconductors now comprises 70-80% of total device costs. Heterogeneous integration and advanced packaging aim to enhance performance while reducing size, weight, power consumption, and costs. Extensive testing and high data integrity are crucial due to the expense of single system failures. Integrated device manufacturers (IDMs) and foundries ensure electrical test coverage to validate semiconductor intellectual property (IP) as “known good” before integration. Advanced packaging and heterogenous integration combines components from various suppliers and technologies. Wafer-probe testing is used for cost-effective validation at the wafer level. Known Good Die (KGD) testing ideally confirms device performance, but it may not always be financially feasible. High data integrity throughout testing stages is essential for confirming chip functionality, preventing the integration of underperforming die into multichip modules.

DATA INTEGRITY DURING PROBE

Wafer-level-test is one of several important test operation, but it is the testing process that is performed pre-assembly. Making it the only opportunity to cost-effectively sort out the “bad-die” prior to back-end-test. Wafer-level testing involves physical contact between all the probes of a probe card (which can range from a few up to 200K pins) and the device-under-test (DUT) to ensure reliable electrical contact during test execution.

A typical wafer-test-cell consists of (1) automated instrument that stimulates and interrogates the DUT(s); (2) a prober which handles & positions a device, provides a thermal environment, and executes probe cleaning; and (3) a probe card which is a customized device-specific interface that provides the electromechanical DUT-to-ATE contact. There are many probe card configurations and contact technologies; however, no single probe card fits all the device testing requirements.

During testing, each touchdown has a significant likelihood of generating particles and adherent materials, which can lead to contamination buildup over time. In-situ probe cleaning addresses issues such as contact resistance (CRES) instability, removes debris affecting probe-to-pad alignment, and maintains uptime for high throughput. To support testing with MEMS-based probe technologies, the industry has developed highly engineered cleaning materials to ensure optimal performance.

For the most advanced test applications, MEMS-style micro-cantilever and vertical probe cards are engineered with highly refined tip geometries for stable electrical contact and optimal test yields. The more damage to the pad created by a contactor, the higher the risk of defects or damage to underlying structures and circuits. Ultra-low force requirements are essential to support zero-defect manufacturing, known-good-die determination, and high parallelism, even after multiple insertions at the same pad location. For instance, large array memory probe cards can have up to 150,000 probes, exerting a force of more than 450 kilograms over a 300mm probing area within the prober.

First-pass-yield and OEE loss occur during continuous probing without a probe tip cleaning process. Polymer-based materials are commonly used to clean large array microcantilever probes during wafer-level testing of memory and automotive devices. Efficient probe-card cleaning is vital for maintaining data integrity, stable yields, and optimized tool uptime. This ensures that only functional dies are integrated, boosting overall yield. Given the commercial value and ASP of devices, improvements in yield and test cost reductions can significantly increase net revenue. For example, a 1% yield increase can result in an annual profit gain of $150 million for a leading-edge logic fab and $110 million for a NAND fab.

Gel-Pak’s probecard cleaning materials enhance first pass yields, throughput, and reduce prober die time during wafer tests. Effective CRES and contamination control improve test efficiency and limit retests. Data analytics support cost-effective strategies from wafer probe to system-level tests, ensuring high yields and reliable data. Early device tests for known good die (KGD) using heterogeneous technologies are essential for binning and die matching.